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general description the MAX4822?ax4825 8-channel relay drivers offer built-in kickback protection and drive +3v/+5v non- latching or dual-coil-latching relays. each independent open-drain output features a 2.7 ? (typ) on-resistance and is guaranteed to sink 70ma (min) of load current. these devices consume less than 300? (max) quies- cent current and have 1? output off-leakage current. a zener-kickback-protection circuit significantly reduces recovery time in applications where switching speed is critical. the MAX4822/max4824 feature a unique power-save mode where the relay current, after activation, can be reduced to a level just above the relay hold-current threshold. this mode keeps the relay activated while significantly reducing the power consumption. the MAX4822/max4823 feature a 10mhz spi-/ qspi-/microwire-compatible serial interface. input data is shifted into a shift register and latched to the outputs when cs transitions from low to high. each data bit in the shift register corresponds to a specific output, allowing independent control of all outputs. the max4824/max4825 feature a 4-bit parallel-input interface. the first 3 bits (a0, a1, a2) determine the out- put address, and the fourth bit (lvl) determines whether the selected output is switched on or off. data is latched to the outputs when cs transitions from low to high. the MAX4822?ax4825 feature separate set and reset functions, allowing turn-on or turn-off of all outputs simultaneously with a single control line. built-in hys- teresis (schmidt trigger) on all digital inputs allows these devices to be used with slow-rising and falling signals, such as those from optocouplers or rc power- up initialization circuits. the MAX4822?ax4825 are available in space-saving 4mm x 4mm, 20-pin thin qfn packages. they are specified over the -40? to +85? extended temperature range. applications ate equipment dsl redundancy protection (adsl/vdsl/hdsl) t1/e1 redundancy protection t3/e3 redundancy protection industrial equipment test equipment (oscilloscopes, spectrum analyzers) features ? built-in zener kickback protection for fast recovery ? programmable power-save mode reduces relay power consumption (MAX4822/max4824) ? 10mhz spi-/qspi-/microwire-compatible serial interface ? eight independent output channels ? drive +3v and +5v relays ? guaranteed 70ma (min) coil drive current ? guaranteed 5 ? (max) r on ? set / reset functions to turn on/off all outputs simultaneously ? serial digital output for daisy chaining ? optional parallel interface (max4824/max4825) ? low 300? (max) quiescent supply current ? space-saving, 4mm x 4mm, 20-pin tqfn package MAX4822?ax4825 +3.3v/+5v, 8-channel relay drivers with fast recovery time and power-save mode ________________________________________________________________ maxim integrated products 1 ordering information 19-3789; rev 0; 8/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package package code MAX4822 etp -40? to +85? 20 tqfn-ep* t2044-3 max4823 etp -40? to +85? 20 tqfn-ep* t2044-3 max4824 etp -40? to +85? 20 tqfn-ep* t2044-3 max4825 etp -40? to +85? 20 tqfn-ep* t2044-3 * for maximum heat dissipation, packages have an exposed pad (ep) on the bottom. solder exposed pad to gnd. pin configurations appear at end of data sheet. spi is a trademark of motorola, inc. qspi is a trademark of motorola, inc. microwire is a trademark of national semiconductor corp. part interface power save MAX4822 serial yes max4823 serial no max4824 parallel yes max4825 parallel no selector guide
MAX4822?ax4825 +3.3v/+5v, 8-channel relay drivers with fast recovery time and power-save mode 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc ........................................................................-0.3v to +6.0v out_ ......................................................................-0.3v to +11v cs , sclk, din, set , reset , a0, a1, a2, lvl......-0.3v to +6.0v dout..........................................................-0.3v to (v cc + 0.3v) psave ........................................................-0.3v to (v cc + 0.3v) continuous out_ current (all outputs turned on) ............150ma continuous out_ current (single output turned on) ........300ma continuous power dissipation (t a = +70?) 20-lead thin qfn (derate 16.9mw/? above +70?) ..1350mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? soldering temperature (10s) ...........................................+300? electrical characteristics (v cc = +2.7v to +5.5v, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = 2.7v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units operating voltage v cc 2.3 5.5 v v cc = 3.6v 160 300 quiescent current i cc i out_ = 0, logic inputs = 0 or v cc v cc = 5.5v 180 300 ? v cc = 3.6v 1.2 dynamic supply current i d f sclk =10mhz, c dout = 50pf v cc = 5.5v 1.6 ma power-save disable threshold (note 2) +130 thermal shutdown output disable threshold (note 3) +150 ? power-on reset transform from high voltage to low voltage 0.6 1.2 2.0 v power-on reset hysteresis 140 mv digital inputs (sclk, din, cs , lvl, a0, a1, a2, reset , set ) v cc = 2.7v to 3.6v 2.0 input logic-high voltage v ih v cc = 4.2v to 5.5v 2.4 v v cc = 2.7v to 3.6v 0.6 input logic-low voltage v il v cc = 4.2v to 5.5v 0.8 v input logic hysteresis v hyst 150 mv input leakage current i leak input voltages = 0 or 5.5v -1.0 +0.01 +1.0 ? input capacitance c in 5pf digital output (dout) dout low voltage v ol i sink = 6ma 0.4 v dout high voltage v oh i source = 0.5ma v cc - 0.5 v
MAX4822?ax4825 +3.3v/+5v, 8-channel relay drivers with fast recovery time and power-save mode _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = +2.7v to +5.5v, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = 2.7v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units relay output drivers (out1?ut8) ps = 001 0.65 x v cc 0.7 x . v cc 0.75 x v cc ps = 010 0.55 x v cc 0.6 x v cc 0.65 x v cc ps = 011 0.45 x v cc 0.5 x v cc 0.55 x v cc ps = 100 0.35 x v cc 0.4 x v cc 0.45 x v cc ps = 101 0.25 x v cc 0.3 x v cc 0.35 x v cc ps = 110 0.15 x v cc 0.2 x v cc 0.25 x v cc out_ drive voltage, power-save on (MAX4822) v outps_ v cc = 2.7v (note 4) ps = 111 0.05 x v cc 0.1 . x v cc 0.15 x v cc v out_ drive voltage, power-save on (max4824) v outps_ v cc = 2.7v (note 4) 0.35 x v cc 0.4 x v cc 0.45 x v cc v out_ on-resistance r on v cc = 2.7v, i out_ = 70ma 2.7 5.0 ? out_ off-leakage current i leak v out_ = v cc , all outputs off -1 +1 ? zener clamping voltage v clamp i out_ = 70ma (note 5) 7.0 9 10.5 v spi timing (MAX4822/max4823) turn-on time (out_) t on from rising edge of cs , r l = 50 ? , c l = 50pf 1.0 ? turn-off time (out_) t off from rising edge of cs , r l = 50 ? , c l = 50pf 3.0 ? sclk frequency f sclk 010 mhz cycle time t ch + t cl 100 ns cs fall-to-sclk rise setup t css 50 ns cs rise-to-sclk hold t csh 50 ns sclk high time t ch 40 ns sclk low time t cl 40 ns data setup time t ds 20 ns
MAX4822?ax4825 +3.3v/+5v, 8-channel relay drivers with fast recovery time and power-save mode 4 _______________________________________________________________________________________ note 1: specifications at -40? are guaranteed by design and not production tested. note 2: thermal shutdown disables power save from all channels to reduce power dissipation inside the device. note 3: thermal shutdown turns off all channels. note 4: the circuit can set the output voltage in power-save mode only if i out x r on < v outp . note 5: after relay turn-off, inductive kickback can momentarily cause the out_ voltage to exceed v cc . this is considered part of normal operation and does not damage the device. note 6: guaranteed by design. note 7: for other capacitance values, use the equation t ps = 32 x c. electrical characteristics (continued) (v cc = +2.7v to +5.5v, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = 2.7v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units data hold time t dh 0ns 50% of sclk to (v ih , v il of d in ), sclk fall to dout valid t do c l = 50pf 17 28 ns rise time (din, sclk, cs , set , reset ) t scr 20% of v cc to 70% of v cc , c l = 50pf (note 6) 2s fall time (din, sclk, cs , reset , set ) t scf 20% of v cc to 70% of v cc , c l = 50pf (note 6) 2s reset minimum pulse width t rw 70 ns set minimum pulse width t sw 70 ns cs minimum pulse width t csw 40 ns parallel timing (max4824/max4825) turn-on time t on from rising edge of cs , r l = 50 ? , c l = 50pf 1s turn-off time t off from rising edge of cs , r l = 50 ? , c l = 50pf 3s lvl setup time t ls 20 ns lvl hold time t lh 0ns address to cs setup time t as 20 ns address to cs hold time t ah 0ns rise time (a2, a1, a0, lvl) t scr 20% of v cc to 70% of v cc , c l = 50pf (note 6) 2s fall time (a2, a1, a0, lvl) t scf 20% of v cc to 70% of v cc , c l = 50pf (note 6) 2s reset pulse width t rw 70 ns set pulse width t sw 70 ns cs minimum pulse width t csw 40 ns power-save timing (MAX4822/max4824) power-save delay time t ps variation from typical value, c l = 100nf (note 7) 1.6 3.2 5.4 ms minimum psave low time to power-save reset t psr 2 3.5 ms
MAX4822?ax4825 +3.3v/+5v, 8-channel relay drivers with fast recovery time and power-save mode _______________________________________________________________________________________ 5 quiescent supply current vs. supply voltage MAX4822-25 toc01 supply voltage (v) supply current ( a) 5.1 4.7 2.7 3.1 3.5 3.9 4.3 145 150 155 160 165 170 175 180 140 2.3 5.5 all channels off quiescent supply current vs. temperature MAX4822-25 toc02 temperature ( c) supply current ( a) 60 35 10 -15 110 120 130 140 150 160 170 180 190 200 100 -40 85 v cc = 5.5v v cc = 2.3v v cc = 3.3v v cc = 5.0v 0.20 0.60 0.40 1.20 1.00 0.80 1.60 1.80 1.40 2.00 145 23 678910 dynamic supply current vs. frequency MAX4822-25 toc03 frequency (mhz) dynamic supply current (ma) c dout = 50pf v cc = 5.5v v cc = 3.6v quiescent supply current vs. logic-input voltage MAX4822-25 toc04 logic-input voltage (v) supply current ( a) 4 3 2 1 100 200 300 400 500 600 700 800 900 1000 1100 0 05 all logic inputs connected v cc = 5.5v v cc = 3.3v on-resistance vs. supply voltage MAX4822-25 toc05 supply voltage (v) r on ( ? ) 5.1 4.7 2.7 3.1 3.5 3.9 4.3 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 1.50 2.3 5.5 i out_sink = 70ma on-resistance vs. temperature MAX4822-25 toc06 temperature ( c) r on ( ? ) 60 35 10 -15 2.0 2.5 3.0 3.5 4.0 1.5 -40 85 v cc = 5.5v v cc = 2.3v v cc = 3.3v v cc = 5.0v i out-sink = 70ma power-on reset voltage vs. temperature MAX4822-25 toc07 temperature ( c) power-on reset voltage (v) 60 35 10 -15 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.00 -40 85 output off-leakage current vs. supply voltage MAX4822-25 toc08 supply voltage (v) output off-leakage (pa) 5.1 4.7 4.3 3.9 3.5 3.1 2.7 1 2 3 4 5 6 0 2.3 5.5 output off-leakage current vs. temperature MAX4822-25 toc09 temperature ( c) output off-leakage (na) 60 35 10 -15 0.01 0.1 1 10 0.001 -40 85 2.3v, 3.3v, 5.0v, and 5.5v t ypical operating characteristics (v cc = 3.3v, t a = +25?, unless otherwise noted.)
MAX4822?ax4825 +3.3v/+5v, 8-channel relay drivers with fast recovery time and power-save mode 6 _______________________________________________________________________________________ out_ turn-on delay time vs. supply voltage MAX4822-25 toc10 supply voltage (v) i on delay time (ns) 5.1 4.7 4.3 3.9 3.5 3.1 2.7 40 60 80 100 120 140 20 2.3 5.5 out_ turn-off delay time vs. supply voltage MAX4822-25 toc11 supply voltage (v) i off delay time (ns) 5.1 4.7 4.3 3.9 3.5 3.1 2.7 600 800 1000 1200 1400 1600 400 2.3 5.5 input-logic threshold vs. supply voltage MAX4822-25 toc12 supply voltage (v) input-logic threshold (v) 5.1 4.7 3.9 4.3 3.1 3.5 2.7 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 1.0 2.3 5.5 back emf clamping with standard 3v relay v cc = 3.3v MAX4822-25 toc13 100 s/div 0v 0v cs 5v/div vout 2v/div power-save delay time vs. capacitance MAX4822-25 toc14 capacitance (nf) t ps (ms) 800 600 200 400 5 10 15 20 30 25 35 40 0 0 1000 v cc = 3.3v power-save delay time vs. supply voltage MAX4822-25 toc15 supply voltage (v) t ps (ms) 5.1 4.7 3.9 4.3 3.1 3.5 2.7 3.55 3.60 3.65 3.70 3.75 3.80 3.85 3.90 3.95 4.00 3.50 2.3 5.5 c psave = 0.1 f 0.3 0.4 0.6 0.5 0.7 0.8 0 100 50 150 200 250 300 output voltage vs. output current in power-save mode (psave register = 111) MAX4822 toc16 output current (ma) output voltage (v) t ypical operating characteristics (continued) (v cc = 3.3v, t a = +25?, unless otherwise noted.)
MAX4822?ax4825 +3.3v/+5v, 8-channel relay drivers with fast recovery time and power-save mode _______________________________________________________________________________________ 7 MAX4822/max4823 pin description pin MAX4822 max4823 name function 11 reset reset input. drive reset low to clear all latches and registers (all outputs are high impedance). reset overrides all other inputs. if reset and set are pulled low at the same time, then reset takes precedence. 22 cs chip-select input. drive cs low to select the device. when cs is low, data at din is clocked into the shift register on sclk? rising edge. drive cs from low to high to latch the data to the registers and activate the relay outputs. 33 din serial data input 44 sclk serial clock input 55 dout serial data output. dout is the output of the shift register. dout can be used to daisy- chain multiple MAX4822/max4823 devices. the data at dout appears synchronous to sclk? falling edge. 6 6, 13 n.c. no connection. not internally connected. 77 gnd ground 88 out8 open-drain output 8. connect out8 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 99 out7 open-drain output 7. connect out7 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 10, 16 10, 16 pgnd power ground. pgnd is a return for the output sinks. connect pgnd pins together and to gnd. 11 11 out6 open-drain output 6. connect out6 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 12 12 out5 open-drain output 5. connect out5 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 13 psave power-save control. connect a timing capacitor from psave to ground. the capacitor value determines power-save timing as explained under the applications information section. psave can also be driven externally to control power-save mode asynchronously. when asserted high, psave reduces the current to all active outputs as determined by the power-save configuration register (see figure 1). to disable power- save mode in all channels, drive psave low for at least 3ms after the last output setting. 14 14 out4 open-drain output 4. connect out4 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 15 15 out3 open-drain output 3. connect out3 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 17 17 out2 open-drain output 2. connect out2 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 18 18 out1 open-drain output 1. connect out1 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance.
MAX4822?ax4825 +3.3v/+5v, 8-channel relay drivers with fast recovery time and power-save mode 8 _______________________________________________________________________________________ pin MAX4822 max4823 name function 19 19 v cc input supply voltage. bypass v cc to gnd with a 0.1? capacitor. 20 20 set set input. drive set low to set all latches and registers high (all outputs are low impedance). set overrides all parallel and serial control inputs. reset overrides set under all conditions. ep ep ep exposed pad. connect exposed paddle to gnd. pin max4824 max4825 name function 11 reset reset input. drive reset low to clear all latches and registers (all outputs are high impedance). reset overrides all other inputs. if reset and set are pulled low at the same time, then reset takes precedence. 22 cs chip-select input. drive cs low to select the device. the cs falling edge latches the output address (a0, a1, a2). the cs rising edge latches level data (lvl). 33 lvl level input. lvl determines whether the selected address is switched on or off. logic- high on lvl switches on the addressed output. a logic-low on lvl switches off the addressed output. 44 a0 digital address 0 input. (see figure 3 for address mapping.) 55 a1 digital address 1 input. (see figure 3 for address mapping.) 66 a2 digital address 2 input. (see figure 3 for address mapping.) 77 gnd ground 88 out8 open-drain output 8. connect out8 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 99 out7 open-drain output 7. connect out7 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 10, 16 10, 16 pgnd power ground. pgnd is a return for the output sinks. connect pgnd pins together and to gnd. 11 11 out6 open-drain output 6. connect out6 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 12 12 out5 open-drain output 5. connect out5 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. MAX4822/max4823 pin description (continued) max4824/max4825 pin description
detailed description serial interface (MAX4822/max4823) depending on the MAX4822/max4823 device, the serial interface can be controlled by either 8- or 16-bit words as depicted in figures 1 and 2. the max4823 does not support power-save mode, so the serial interface con- sists of an 8-bit-only shift register for faster control. the MAX4822 consists of a 16-bit shift register and par- allel latch controlled by sclk and cs . the input to the shift register is a 16-bit word. in the MAX4822, the first 8 bits determine the register address and are followed by 8 bits of data as depicted in figure 1. bit a7 corre- sponds to the msb of the 8-bit register address in figure 1, while bit d7 corresponds to the msb of the 8 bits of data in the same figure 1. the max4823 consists of an 8-bit shift register and par- allel latch controlled by sclk and cs . the input to the shift register is an 8-bit word. each data bit controls one of the eight outputs, with the most significant bit (d7) corresponding to out8, and the least significant bit (d0) corresponding to out1 (see figure 2). MAX4822?ax4825 +3.3v/+5v, 8-channel relay drivers with fast recovery time and power-save mode _______________________________________________________________________________________ 9 pin max4824 max4825 name function 13 psave power-save control. connect a timing capacitor from psave to ground. the capacitor value determines power-save timing as explained under the applications information section. psave can also be driven externally to control power-save mode asynchronously. when psave is asserted high, the current through the coils is reduced to 60% of the initial nominal current value. to disable power-save mode in all channels, drive psave low for at least 3ms after last output setting. 14 14 out4 open-drain output 4. connect out4 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 15 15 out3 open-drain output 3. connect out3 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 17 17 out2 open-drain output 2. connect out2 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 18 18 out1 open-drain output 1. connect out1 to the low side of a relay coil. this output is pulled to pgnd when activated, but otherwise is high impedance. 19 19 v cc input supply voltage. bypass v cc to gnd with a 0.1? capacitor. 20 20 set set input. drive set low to set all latches and registers high (all outputs are low impedance). set overrides all parallel and serial control inputs. reset overrides set under all conditions. ? 3 n.c. no connection. not internally connected. ep ep ep exposed pad. connect exposed paddle to ground. max4824/max4825 pin description (continued)
MAX4822?ax4825 when cs is low (MAX4822/max4823 device is select- ed), data at din is clocked into the shift register syn- chronously with sclk? rising edge. driving cs from low to high latches the data in the shift register (figures 5 and 6). dout is the output of the shift register. data appears on dout synchronously with sclk? falling edge and is identical to the data at din delayed by eight clock cycles for the max4823, or 16 clock cycles for the MAX4822. when shifting the input data, a7 is the first input bit in and out of the shift register for the MAX4822 device. d7 is the first bit in or out of the shift register for +3.3v/+5v, 8-channel relay drivers with fast recovery time and power-save mode 10 ______________________________________________________________________________________ address [a7...a0] active register 00h output control register?utr 01h p o w e r - s a ve c o n fi g u r a ti o n r e g i s t e r ? p s serial-input address map d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 out 8 out 7 out 6 out 5 out 4 out 3 out 2 out 1 msb lsb output control register?ut r (address = 00h) note: setting d n to logic 1 turns on output out n+1 . setting d n to logic 0, turns off out n+1 . example: setting d 2 = 1 turns on out 3 . d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 xxxxxps0ps1ps2 msb lsb power-save configuration register?s (address= 01h) ps0 ps1 ps2 power-save configuration 00 0p ower-save is disabled (default operation) 00 1 power-save is enabled. v out set to 70% of v cc , typical after t ps ms (see note 1), causes i out _ to be reduced to approximately 30%, typical after t ps ms. 01 0 power-save is enabled. v out set to 60% of v cc , typical after t ps ms (see note 1), causes i out _ to be reduced to approximately 40%, typical after t ps ms. 01 1 power-save is enabled. v out set to 50% of v cc , typical after t ps ms (see note 1), causes i out _ to be reduced to approximately 50%, typical after t ps ms. 10 0 power-save is enabled. v out set to 40% of v cc , typical after t ps ms (see note 1), causes i out _ to be reduced to approximately 60%, typical after t ps ms. 10 1 power-save is enabled. v out set to 30% of v cc , typical after t ps ms (see note 1), causes i out _ to be reduced to approximately 70%, typical after t ps ms. 11 0 power-save is enabled. v out set to 20% of v cc , typical after t ps ms (see note 1), causes i out _ to be reduced to approximately 80%, typical after t ps ms. 11 1 power-save is enabled. v out set to 10% of v cc , typical after t ps ms (see note 1), causes i out _ to be reduced to approximately 90%, typical after t ps ms. power-save configuration options note 1: the time period t ps is determined by the capacitor connected to psave. figure 1. 16-bit register map for MAX4822
the max4823 device. if the address a0.a7 is not 00h or 01h, then the outputs and the psave configura- tion register are not updated. the address is stored in the shift register only. while cs is low, the out_ outputs always remain in their previous state. for the max4823, drive cs high after 8 bits of data have been shifted in to update the output state of the max4823, and to further inhibit data from entering the shift register. for the MAX4822, drive cs high after 16 bits of data have been shifted in to update the output state of the MAX4822, and to further inhibit data from entering the shift register. when cs is high, transi- tions at din and sclk have no effect on the output, and the first input bit a7 (or d7) is present at dout. for the MAX4822, if the number of data bits entered while cs is low is greater or less than 16, the shift regis- ter contains only the last 16 bits, regardless of when they were entered. for the max4823, if the number of data bits entered while cs is low is greater or less than 8, the shift register contains only the last 8 data bits, regardless of when they were entered. parallel interface (max4824/max4825) the parallel interface consists of 3 address bits (a0, a1, a2) and one level selector bit (lvl). the address bits determine which output is updated, and the level bit determines whether the addressed output is switched on (lvl = high) or off (lvl = low). when cs is high, the address and level bits have no effect on the state of the outputs. driving cs from low to high latches MAX4822?ax4825 +3.3v/+5v, 8-channel relay drivers with fast recovery time and power-save mode ______________________________________________________________________________________ 11 sclk din dout t css t cl t ch t csw t csh t do t on , t off t ds t dh d7 d6 d1 d0 cs out_ figure 4. 3-wire serial-interface timing diagram a2 a1 a0 output low low low out1 low low high out2 low high low out3 low high high out4 high low low out5 high low high out6 high high low out7 high high high out8 figure 3. register address map for max4824/max4825 msb lsb d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 out 8 out 7 out 6 out 5 out 4 out 3 out 2 out 1 note: setting d n to logic 1 turns on output out n+1 . setting d n to logic 0 turns off output out n+1 . example: setting the d 2 = 1 turns out 3 on. figure 2. 8-bit register map for max4823
MAX4822?ax4825 level data to the parallel register and updates the state of the outputs. address data entered after cs is pulled low is not reflected in the state of the outputs following the next low-to-high transition on cs (figure 7). set/reset functions the MAX4822?ax4825 feature set and reset inputs that allow simultaneous turn-on or turn-off of all outputs using a single control line. drive set low to set all latch- es and registers to 1 and turn all outputs on. set over- rides all serial/parallel control inputs. drive reset low to clear all latches and registers and to turn all outputs off. reset overrides all other inputs including set . power-on reset the MAX4822?ax4825 feature power-on reset. the power-on reset function causes all latches to be cleared automatically upon power-up. this ensures that all outputs come up in the off or high-impedance state. applications information daisy chaining the MAX4822/max4823 feature a digital output (dout) that provides a simple way to daisy chain multi- ple devices. this feature allows driving large banks of relays using only a single serial interface. to daisy chain multiple devices, connect all cs inputs together, and connect the dout of one device to the din of another device (see figure 8). during operation, a stream of serial data is shifted through the MAX4822/ max4823 devices in series. when cs goes high, all outputs update simultaneously. the MAX4822/max4823 can also be used in a slave configuration that allows individual addressing of devices. connect all the din inputs together, and use the cs input to address one device at a time. drive cs low to select a slave and input the data into the shift register. drive cs high to latch the data and turn on the appropriate outputs. typically, in this configuration only one slave is addressed at a time. power-save mode the MAX4822/max4824 feature a unique power-save mode where the relay current, after activation, can be reduced to a level just above the relay hold-current threshold. this mode keeps the relay activated while significantly reducing the power consumption. in serial mode (MAX4822), choose between seven cur- rent levels ranging from 30% to 90% of the nominal cur- rent in 10% increments. the actual percentage is determined by the power-save configuration register (figure 1). in parallel mode (max4824), the power-save current is fixed at 60% of the nominal current. power-save timer every time there is a write operation to the device ( cs transitions from low to high), the MAX4822/max4824 start charging the capacitor connected to psave. the serial power-save implementation is such that a write operation does not change the state of channels already in power-save mode (unless the write turns the channel off). after a certain time period, t ps (determined by the capacitor value), the capacitor reaches a voltage threshold that sets all active outputs to power-save mode. the t ps period should be made long enough to allow the relay to turn on completely. the time period t ps can be adjusted by using different capacitor values +3.3v/+5v, 8-channel relay drivers with fast recovery time and power-save mode 12 ______________________________________________________________________________________ a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 cs sclk din figure 5. 3-wire serial-interface operation for MAX4822
connected to psave. the value t ps is given by the fol- lowing formula: t ps = 32 x c where c is in ? and t ps is in ms. for example, if the desired t ps is 20ms, then the required capacitor value is 20 / 32 = 0.625?. power-save mode accuracy the current through the relay is controlled by setting the voltage at out_ to a percentage of the v cc supply as specified under the electrical characteristics and in the register description. the current through the relay (i out ) depends on the switch on-resistance, r on, in addition to the relay resistance r r according to the fol- lowing relation: i out = v cc / (r on + r r ) the power-save, current-setting i ps depends on the fraction of the supply voltage v cc that is set by the loop depending on the following relation: i ps = v cc - ( x v cc ) / r r therefore: i ps / i out = (1- ) x (1 + r on / r r ) this relation shows how the fraction of reduction in the current depends on the switch on-resistance, as well as from the accuracy of the voltage setting ( ). the higher the r on with respect to r r, the higher the inaccuracy. this is particularly true at low voltage when the relay resistance is low (less than 40 ? ) and the switch can account for up to 10% of the total resistance. in addi- tion, when the supply-voltage setting ( ) is low (10% or 20%) and the supply voltage (v cc ) is low, the voltage drop across the switch (i out x r on ) may already exceed, or may be very close to, the desired voltage- setting value. daisy chaining and power-save mode in a normal configuration using the power-save feature, several MAX4822s can be daisy chained as shown in figure 9. for each MAX4822, the power-save timing t pd (time it takes to reduce the relay current once the relay is actuated) is controlled by the capacitor con- nected to psave. an alternative configuration that eliminates the psave capacitors uses a common psave control line driven by an open-drain n-channel mosfet (figure 10). in this con- figuration, the psave inputs are connected together to asynchronously control the power-save timing for all the MAX4822s in the chain. the ?/? drives the n-channel mosfet low for the duration of a write cycle to the spi chain, plus some delay time to allow the relays to close. (this time is typically specified in the relay data sheet.) once this delay time has elapsed, the n-channel mosfet is turned off, allowing the MAX4822? internal 35? pullup current to raise psave to a logic-high level, activating the power-save mode in all active outputs. mosfet selection in the daisy-chain configuration of figure 10, the n-channel mosfet drives psave low. when the n-channel mosfet is turned off, psave is pulled high by an internal 35? pullup in each MAX4822, and the power-save mode is enabled. because of the paralleled psave pullup currents, the required size of the n-channel mosfet depends upon the number of MAX4822 devices in the chain. determine the size of the n-channel mosfet by the following relation: r on < 1428 / n MAX4822?ax4825 +3.3v/+5v, 8-channel relay drivers with fast recovery time and power-save mode ______________________________________________________________________________________ 13 d7 d6 d5 d4 d3 d2 d1 d0 cs sclk din figure 6. 3-wire serial-interface operation for the max4823 cs a_ lvl v out t as t ah t ls t lh t on , t off figure 7. parallel-interface timing diagram
MAX4822?ax4825 where n is the total number of MAX4822 devices in a single chain, and r on is the on-resistance of the n-channel mosfet in ? s. for example, if n = 10: r on < 142 ? an n-channel mosfet with r on less than 142 ? is required for a daisy chain of 10 MAX4822 devices. inductive kickback protection with fast recovery time the MAX4822?ax4825 feature built-in inductive kick- back protection to reduce the voltage spike on out_ generated by a relay? coil inductance when the output is suddenly switched off. an internal zener clamp allows the inductor current to flow back to ground. the zener configuration significantly reduces the recovery time (time it takes to turn off the relay) when compared to protection configurations with just one diode across the coil. +3.3v/+5v, 8-channel relay drivers with fast recovery time and power-save mode 14 ______________________________________________________________________________________ MAX4822 din din sclk sclk cs dout out8 pgnd cs v cc v cc 0.1 f gnd out1 MAX4822 din sclk dout out8 pgnd cs v cc v cc 0.1 f gnd out1 MAX4822 din sclk psave dout out8 pgnd cs v cc v cc 0.1 f 0.47 f gnd out1 psave 0.47 f psave 0.47 f figure 9. daisy-chained MAX4822s with a capacitor connected to psave max4823 din din sclk sclk cs sclk dout out8 pgnd cs v cc v cc 0.1 f gnd out1 max4823 din sclk dout out8 pgnd cs v cc v cc 0.1 f gnd out1 max4823 din sclk dout out8 pgnd cs v cc v cc 0.1 f gnd out1 sclk figure 8. daisy-chain configuration
MAX4822?ax4825 +3.3v/+5v, 8-channel relay drivers with fast recovery time and power-save mode ______________________________________________________________________________________ 15 MAX4822 din din sclk sclk cs dout out8 pgnd cs v cc v cc v cc 0.1 f gnd out1 MAX4822 din sclk dout out8 pgnd cs v cc v cc 0.1 f gnd out1 MAX4822 din sclk psave dout out8 pgnd cs v cc v cc 0.1 f gnd out1 psave psave n figure 10. daisy-chaining MAX4822s with a psave connected to an n-channel mosfet chip information transistor count: 5799 process: bicmos
MAX4822?ax4825 +3.3v/+5v, 8-channel relay drivers with fast recovery time and power-save mode 16 ______________________________________________________________________________________ MAX4822/max4823 functional diagram (serial interface) MAX4822 max4823 out1 out2 v cc reset control register power-save configuration register shift register set din dout sclk psave cs out3 out4 out5 out6 out7 out8 pgnd MAX4822 only power save on1 psave on2 on3 on4 on5 on6 on7 on8 gnd power- on reset
MAX4822?ax4825 +3.3v/+5v, 8-channel relay drivers with fast recovery time and power-save mode ______________________________________________________________________________________ 17 max4824/max4825 functional diagram (parallel interface) max4824 max4825 out1 out2 v cc reset control register 4-to-8 decoder set lvl a2 a0 a1 psave cs out3 out4 out5 out6 out7 out8 pgnd max4824 only power save on1 psaveon/off on2 on3 on4 on5 on6 on7 on8 gnd
MAX4822?ax4825 +3.3v/+5v, 8-channel relay drivers with fast recovery time and power-save mode 18 ______________________________________________________________________________________ top view 20 19 18 17 set v cc out1 out2 16 pgnd 13 12 11 14 15 out5 psave out4 out3 out6 4 3 2 1 sclk din cs reset 5 dout 6 7 8 9 n.c. gnd out8 out7 10 pgnd MAX4822 thin qfn 20 19 18 17 set v cc out1 out2 16 pgnd 13 12 11 14 15 out5 n.c. out4 out3 out6 4 3 2 1 sclk din cs reset 5 dout 6 7 8 9 n.c. gnd out8 out7 10 pgnd max4823 thin qfn 20 19 18 17 set v cc out1 out2 16 pgnd 13 12 11 14 15 out5 psave out4 out3 out6 4 3 2 1 a0 lvl cs reset 5 a1 6 7 8 9 a2 gnd out8 out7 10 pgnd max4824 thin qfn 20 19 18 17 set v cc out1 out2 16 pgnd 13 12 11 14 15 out5 n.c. out4 out3 out6 4 3 2 1 a0 lvl cs reset 5 a1 6 7 8 9 a2 gnd out8 out7 10 pgnd max4825 thin qfn pin configurations
MAX4822?ax4825 +3.3v/+5v, 8-channel relay drivers with fast recovery time and power-save mode maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 19 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. MAX4822?ax4825 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 24l qfn thin.eps package outline, 21-0139 2 1 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm package outline, 21-0139 2 2 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm

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